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Innovative layout techniques are explored to enhance the electrical performance and radiation tolerance of planar MOSFETs without incurring additional costs in CMOS manufacturing. The book details engineering strategies involving pn junctions and gate layout modifications, introducing effects like Longitudinal Corner Effect and Drain Leakage Current Reduction. Supported by 3D simulations and experimental data, these methods enable designers to meet CMOS IC specifications while significantly improving performance and robustness against ionizing radiation.
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Layout Techniques in MOSFETs, Salvador Pinillos Gimenez
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- Pubblicato
- 2016
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