Tom Shanley Libri

This book details the internal architecture of the Pentium Pro and Pentium II processors, covering their hardware and software characteristics, bus protocols, and overall machine architecture, including the BIOS Update Feature. Aimed at computer hardware and software engineers, it explains how these processors translate legacy x86 code into RISC instructions, execute them out-of-order, and reassemble results to maintain original program flow. It explores the processors' internal operations, transaction types, and bus traffic monitoring for cache consistency. The new edition provides comprehensive coverage of the Pentium II, highlighting differences from the Pentium Pro, such as the Slot 1 connector and processor cartridge design, as well as support for the MMX instruction set and optimizations for 16-bit code execution. It also discusses the Pentium II's L2 cache and power-conservation modes. Additional topics include the relationship of these processors to other processors, PCI bridges, caches, memory, power-on configuration, startup transaction deferral, instruction and register sets, paging, interrupt enhancements, Machine Check Architecture, performance monitoring, and the Time Stamp Counter. The book is part of a series that provides clear, comprehensive guides to key PC hardware standards, illustrating the interplay between software and hardware.